Logic Requirements

Regarding discussion topic

Aaron, thanks for your welcome!
A technology to continue litho for logic manufacturing beyond the limits of single-layer optical litho must have - besides enough resolution - reasonable cost of ownership also for small wafer numbers per mask. This requirement may be somewhat less stringent as some proponents of certain options demand, since there is the widely used option to have 10 or more designs on one mask. And mask cost has been reduced drastically over the lifetime of a technology. But this surely is #1 for logic.

From this perspective, I expect that logic designs will proceed further on the road of restricted design rules, and that EUV will come to logic litho somewhat later than to litho for CPUs or memories.
This also keeps open the opportunity for ebeam direct write. Unfortunately, there are quite some issues to be solved. And that needs money - at least much more, than is currently spent or planned.

Thank you, Wilhelm. So... If e-beam direct write needs more money to resolve technical issues, where do you think that funding should come from? Are logic manufacturers putting much money in that direction?

That's imho the #1 issue: Almost all companies who develop & sell logic circuits have outsourced their manufacturing and with it their lithography to Foundries, and have become fab-less. For competitive reasons, those foundries can charge only a very limited amount of money for long term topics as e.g. lithography development.

Until now, this went well, since other IC flavors do that. But as soon as lithographic requirements start to develop in different directions, this will come up clearly.

Wilhelm, if I may chime in here, I wonder if you think the throughput targets in play for the various EBDW efforts are reasonable.

Good point, Franklin!
That's why I like very much the proposal to use EBDW tools ftb just for 2nd layer exposure, where a few high-resolution exposures cut the highly regular pattern of the 1st exposure (by 193nm) into a usefull layout.

Wilhelm, do you see any opportunities for nanoimprint in logic manufacturing? It seems that if there's any chance at all within mainstream manufacturing, the interest has come more from the memory makers.

What are the downsides to NIL that are specific to logic? And/or the benefits?

One big issue in logic is the considerable time & effort you need to make sure that a certain non-working functionality in every chip is caused by a mask printing error, and not by some design glitch like wrong timing of signals. Mask defects in NIL, which may be present for some exposures, but disappear again, are far easier handled by a regular design with redundances - like DRAMs etc.

Besides that, will a 1x NIL-template much cheaper than an EUV mask?