Depending on the design of the LED – lateral, vertical, flip chip or thin film flip chip – and efficiency of the fabricated LED chip, the complexity of the photolithography increases to up to 8 mask levels to be aligned accurately.
Obviously, tight alignment accuracy is needed to conserve as much GaN heterostructure and limit the shadowing of stacked metal and passivation layers. In order to achieve this, the major hurdle is the very low visibility of the etched structures and therefore alignments marks, since both GaN and sapphire are optically transparent.
There are many similarities between today’s 2, 3 and 4-in Sapphire processes and the silicon processes used in the 80’s and 90’s on 2, 3 and 4-in silicon wafers. Critical dimensions are about the same as the silicon-based processes for logic device of that time frame (2 to 3 microns today for the PSS layer). Imaging these linewidths typically requires a transition to projection lithography to minimize defects and improve device yield, which was a driving factor in the silicon processes adopting stepper technology.
What level of yield improvement that can be expected with the adoption of relevant silicon processes may vary greatly depending on the LED device design rules and performance specifications, but can be significant. Yield improvements of 5 percent or more have been demonstrated with the implementation of projection lithography on the most critical HBLED lithography levels.
Depending on the design of the LED – lateral, vertical, flip chip or thin film flip chip – and efficiency of the fabricated LED chip, the complexity of the photolithography increases to up to 8 mask levels to be aligned accurately.
Obviously, tight alignment accuracy is needed to conserve as much GaN heterostructure and limit the shadowing of stacked metal and passivation layers. In order to achieve this, the major hurdle is the very low visibility of the etched structures and therefore alignments marks, since both GaN and sapphire are optically transparent.
Is this an area where LEDs can learn from mainstream silicon processes? What level of percentage improvement can we expect in yield going forward?
There are many similarities between today’s 2, 3 and 4-in Sapphire processes and the silicon processes used in the 80’s and 90’s on 2, 3 and 4-in silicon wafers. Critical dimensions are about the same as the silicon-based processes for logic device of that time frame (2 to 3 microns today for the PSS layer). Imaging these linewidths typically requires a transition to projection lithography to minimize defects and improve device yield, which was a driving factor in the silicon processes adopting stepper technology.
What level of yield improvement that can be expected with the adoption of relevant silicon processes may vary greatly depending on the LED device design rules and performance specifications, but can be significant. Yield improvements of 5 percent or more have been demonstrated with the implementation of projection lithography on the most critical HBLED lithography levels.
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