It was my pleasure this week to attend a lecture by none other than Daniel Abrams, a founder and formerly CTO of Luminescent. This company has developed a set of algorithms for calculating precise pattern corrections necessary for printing random logic images at dramatically sub-wavelength dimensions with manufacturable process margins. This computationally aggressive OPC (Optical Proximity Correction) strategy, termed “inverse lithography”, is poised to revolutionize masking strategies and extend the lifespan of optical lithography. [1]
OPC itself has been around a long time. In its simplest form, one can approach OPC as merely adjusting the mask to print the shape desired in the silicon. If at final check the line-end is too short and thin, the mask is adjusted by making the line end thicker and longer than originally designed to compensate. This correction strategy can be augmented by rules developed with experience and application of optical principles. Added lobes at line ends (“serfs”, “hammer heads”, etc.) and sub-resolution lines next to linear features (“scatter bars”) and other Sub Resolution Assist Features (SRAFs) are now becoming routine for the improvement of mask and process capability. [2]
While rule based OPC has been very successful, even more impressive results may be obtained for computationally derived OPC (so called “inverse lithography”). Substantially improved margins have been shown in the past for 90nm, 65nm and 45nm nodes, however in this lecture, 32nm node results were shown. Abrams’ presentation was compelling, showing impressive process margins obtainable at the 32nm node by Luminescent and their collaborators.
Their approach treats the OPC problem as a set of continuous functions derived from Maxwell’s equations for the optics, with parametric correction terms added for the mask, resist and etch processes. This is facilitated through the representation of the 2-dimensional mask image as a 3 dimensional surface, enabling shorter computational times and manageable required computational resources [3, 4]
Early on this approach was challenged by concerns for manufacturability. However research and development results prove the practicality of the approach. Approaches to improving computational speed and manufacturing were developed, including algorithms to find repeated geometries (“redundancy”). [5]
Intel Corporation has publicly disclosed a least some of its work on computational OPC. Recently, this has been discussed in the context of post 32nm node insertion and uses a “pixilated” approach. [6, 7] The combination of the computational OPC approach with double patterning is an obvious direction, since neither strategy precludes the other and adds substantial synergy. Recently Yan Borodovsky of Intel and his collaborators at Sant Cruz, Amyn Poonawala and Peyman Milanfar describe printing tests of just such an approach rending 60nm silicon structures. [8] Other players in this field include Mentor Graphics, Brion and, of course, IBM [9, 10, 11]