What simulation capabilities will be required to support 3D IC process development?
Ric - what types of simulation capabilities do we feel are necessary to support 3D IC process development? Has Synopsys been working on tools to address these needs?
The short term best help would be an extractor that can deal with multiple layers of silicon. This would take some of the raw estimation that we need to do today out of SPICE simulation. Eventually, I think thermal and electrial 3D modeling will be required for large, complex 3D logic or logic-memory combinations.
Indeed. We’ve been
developing tools to address several key areas of 3D IC process development. A
key area is simulating the stresses generating in and around the TSV. The
concern here is twofold: high stress points could lead to reliability problems
such delamination of material interfaces, etc., and the stress generated in the
silicon affects the mobility of the electrons and holes in the vicinity of the
TSV which, as we know from strained silicon technology, has an impact on the
drive current and performance. More recently we’ve also been looking at
detailed modeling of the deep trench etching and seed liner deposition inside
the TSV. The reason for this is that as the via diameters get smaller it
becomes more difficult to etch deep vias, so using simulation to understand how
to optimize this process and control it in a manufacturing environment look
like and emerging concern. There is also the design-oriented concern of
computing the TSV parasitic capacitance and resistance as input into extraction
and circuit simulation tools for calculating accurate path delays. So I agree
with Bob when he referred to 3D electrical extraction as a need. Fortunately, this
is a relatively straightforward problem since it’s not that different from
traditional parasitic extraction and is well addressed with proven field
solvers.
Hi Françoise,
Indeed. We’ve been developing tools to address several key areas of 3D IC process development. A key area is simulating the stresses generating in and around the TSV. The concern here is twofold: high stress points could lead to reliability problems such delamination of material interfaces, etc., and the stress generated in the silicon affects the mobility of the electrons and holes in the vicinity of the TSV which, as we know from strained silicon technology, has an impact on the drive current and performance. More recently we’ve also been looking at detailed modeling of the deep trench etching and seed liner deposition inside the TSV. The reason for this is that as the via diameters get smaller it becomes more difficult to etch deep vias, so using simulation to understand how to optimize this process and control it in a manufacturing environment look like and emerging concern. There is also the design-oriented concern of computing the TSV parasitic capacitance and resistance as input into extraction and circuit simulation tools for calculating accurate path delays. So I agree with Bob when he referred to 3D electrical extraction as a need. Fortunately, this is a relatively straightforward problem since it’s not that different from traditional parasitic extraction and is well addressed with proven field solvers.