How should 3D ICs be tested, and what difficulties does this present?
Contact issues, known good die, and quality assurance have all been identified as test issues that need to be addressed with 3D ICs. Bob and/or Sitaram, can you offer your perspective on how 3D ICs should be tested, and what difficulties does this present?
With circuit level 3D, you can't do device layer testing. We have >1M interconnect per die. This is like a discussion about testing a die prior to metal one to see with it is worthwhile putting the metal down... not possible. So the approach we use is improved scribe lane test structures and rigorous redundancy. The custom scribe lane structures allow us to qualify the general wafer quality as well as do speed binning. This also means we don't need to touch the pads that will be used for bonding. Virtually any probe damage significantly compromises the ultimate yield.
Redundancy is only as required in 3D as in 2D. If the 3D device has 100 sqmm of accumulated silicon area, it will yield about the same as a 100 sqmm 2D device. Of course many people including ourselves want to build several hundred or more sqmm parts in 3D. To do this you need to practice good if not exceptional repair and redundancy. We believe this in the future will be a requirement not only of memories but most logic also. Already we see 3 processor die from AMD (and Intel?). I expect that chips with 9 built cores sold as 8 functional cores will be the norm.
As far as KGD, I like the term, kinda good die. As the complexity goes up, I/O counts increase, and we press the speed limitations of the interconnect more, known good die will be more and more out of reach.
Designers need to come to terms with a paradigm shift where future yield will rely heavily on how repairable and fault tolerant your design is. A 15nm 2D IC with 10 billion gates will have zero yield just as surely as a 45nm 3D version.
So if I understand correctly, you advocate repair and redundancy as an alternative to traditional probe testing, to avoid contacting the bond pads? What about the possibility of contact-free prob testing? Has there been any work done in that area?
Contact free solves part of the problem. and there are at least two or three groups working on this. I think this is a good and necessary approach of I/O level 3D interconnect, but with circuit level 3D the issue is the number of signals. Testing thousands much less millions of I/O is just not possible.
With circuit-level 3D, device layer testing isn't
possible due to the number of interconnects per die numbering in the millions.
What Bob Patti recommends is a self-test and repair approach. He says designers
should be ready for a paradigm shift where future yield relies on how
repairable and fault tolerant your design, rather than KDG. On the other hand,
I/O level 3D interconnect will benefit from work being done by probe testing
companies developing contact-free probe technologies. There are reportedly 2 or 3 groups working on
this.
With circuit level 3D, you can't do device layer testing. We have >1M interconnect per die. This is like a discussion about testing a die prior to metal one to see with it is worthwhile putting the metal down... not possible. So the approach we use is improved scribe lane test structures and rigorous redundancy. The custom scribe lane structures allow us to qualify the general wafer quality as well as do speed binning. This also means we don't need to touch the pads that will be used for bonding. Virtually any probe damage significantly compromises the ultimate yield.
Redundancy is only as required in 3D as in 2D. If the 3D device has 100 sqmm of accumulated silicon area, it will yield about the same as a 100 sqmm 2D device. Of course many people including ourselves want to build several hundred or more sqmm parts in 3D. To do this you need to practice good if not exceptional repair and redundancy. We believe this in the future will be a requirement not only of memories but most logic also. Already we see 3 processor die from AMD (and Intel?). I expect that chips with 9 built cores sold as 8 functional cores will be the norm.
As far as KGD, I like the term, kinda good die. As the complexity goes up, I/O counts increase, and we press the speed limitations of the interconnect more, known good die will be more and more out of reach.
Designers need to come to terms with a paradigm shift where future yield will rely heavily on how repairable and fault tolerant your design is. A 15nm 2D IC with 10 billion gates will have zero yield just as surely as a 45nm 3D version.
Regarding #1
So if I understand correctly, you advocate repair and redundancy as an alternative to traditional probe testing, to avoid contacting the bond pads? What about the possibility of contact-free prob testing? Has there been any work done in that area?
Discussion Summary
With circuit-level 3D, device layer testing isn't possible due to the number of interconnects per die numbering in the millions. What Bob Patti recommends is a self-test and repair approach. He says designers should be ready for a paradigm shift where future yield relies on how repairable and fault tolerant your design, rather than KDG. On the other hand, I/O level 3D interconnect will benefit from work being done by probe testing companies developing contact-free probe technologies. There are reportedly 2 or 3 groups working on this.