We installed first 200mm tools for 3D-IC research in 1999 at universities and for industrial R&D.
Looking back we expected everything to happen faster. But looking at other examples of "invent - innovate - implement" phases, 10 years is rather typical. We experienced similar cycles for MEMS getting in consumer products or SOI.
Until recently the major drivers for3D-IC, performance and formfactor, were simply achieveable with conventional scaling and packaging technologies.
Important milestones on the way from university to industry were 3D ITRS roadmaps and engagement from industry funded research. The great production oriented programs like the ones of Sematech, Leti, IMEC or major IDMs are required to mature the technology for HVM and create a support infrastructure.
Each of these milestones could have happened maybe 2 years sooner.
As an equipment manufacturer I could say this delay mainly occured by finding budgets for the tools
How about processes and solutions for thin wafer handling, and temporary bonding and debonding? Thisis one area identified as still needing viable solutions before market adoption can be achieved. I know you must have some opinions here.
The handling of thinned wafers on rigid carriers was first used in volume at compound semiconductor houses and for Si based power devices. In the CMOS world thinning is mainly accomplished with backgrinding tape on large inline systems. We introduced the idea of a rigid carrier for CMOS to enable backside processing on standard equipment.
About 5 years ago we became already experts in bonding and debonding with a variety of different materials (adhesives) - driven by specific customer requirements.
However in no other process technology we learned more about process integration: The challenges did not occur in the bonding and debonding step but rather the process steps inbetween.
The compatibility of the bonded stack had to be proven for each individual customer process flow.
To meet this challenge we decided around 2004:
a) To work closer with one material supplier - Brewer Science. The close cooperation over the past years resulted in new high temperature and high topography capable materials.
b) Focus on process integration: We converted our demo facilities around the world to more independent business units offering process development and pilot line manufacturing. During the process development we can adapt the temporary bond to the customers needs and if required come up with modifications of hardware, software or material. Customers then can run pilot line volume for qualification in a virtual line before investing in equipment.
Today we offer the EVG850 Series Bonders and Debonders as 2 modular platforms for either 200mm or 300mm wafers. Several 300mm equipment sets are already installed worldwide.
A newer focus area is qualification of temporary bonds for subsequent Chip-to-Wafer or Wafer-to-Wafer stacking processes as they occur for example in the EMC-3D process flow http://www.emc3d.org/flow.html
I'm sure you're aware that SUSS MicroTec has promoted their latest bonding and debonding system asbeing configurable to several different material processes that exist in the market, including 3M and TMAT's processes. Can you explain EVG's strategy of working only with one supplier to achieve this?
Our equipment is modular and can be configured to work with a variety of materials. For example we have many users in production with dry laminated adhesive tapes and proprietary spin on adhesives. We still support this - but out of the past years work we recommend the best material / process technology available today from Brewer Science.
So why did we decide to select and focus our efforts?
We were 5 years ago at that stage: A list of materials available, all compatible and qualified on our equipment, but frequently none of them fully compatible to the process integration requirement of our customer.
So we decided to change this by teaming up with Brewer in order to develop new materials for the best process integration. Out of this development customers have access to (in my opinion) the best material solution available today.
The success we had in the last years with bonding / debonding equipment proves this strategy and is a good foundation for future challenges.
Also I firmly believe that discussing the same usually confidential requirement with several (at the end of the day competing) material suppliers is an interesting concept, but could be difficult to maintain in the long run.
To add to the discussion, I believe that there are (were?) two issues. The first was that the existing solutions were adequate and there was a roadmap for scaling them. The fear factor was low. Secondly, if one had to chose a 3D technology, there were just too many options to pick from, and not enough critical mass around them. This made it difficult to select one option and drive it to HVM.
This is beginning to change. We now need EUV, high k dielectrics, Finfets and low k dielectrics to stay on the scaling roadmap. Introducing one new element in HVM is challenging enough, and the prospect of introducing several simulaneously is daunting. The fear factor is higher and new technology is necessary. In addition, people have thought more about the options and what suits their product offerings best, and the options are being narrowed.
Looking at the discussion thread between both of you, I think of porous low k dielectric development. At SEMATECH, we evaluated several new materials, but the technology started to become real when each tool supplier began providing a material solution to accompany their equipment platform. The EVG-Brewer and Suss-3M collaborations seem very similar. The advantage to the users is that the burden of developing the material-equipment solution now rests with the supplier(s) and they can focus more on the integration.
Perhaps a better
question is whether 3D IC technology is being delayed at all, or just moving
along as historically expected. A 10 year cycle from development to
implementation is not unusual in this industry. Paul Lindner of EV Group notes that until
recently, major drivers for 3D-IC were achievable
with conventional scaling and packaging technologies. Sitram Arkalgud adds to this the many options
for 3D integration processes to pick from, and not enough critical mass around
them. This made it difficult to select one option and drive it to high volume
manufacturing.
Specifically
concerning recent collaborative developments in tools and materials processes
for temporary bonding and debonding processes, Arkalgud notes that from SEMATECH’s
perspective, the advantage to the users is that the burden of developing
the material-equipment solution now rests with the supplier(s) and they (users)
can focus more on the integration process flow.
We installed first 200mm tools for 3D-IC research in 1999 at universities and for industrial R&D.
Looking back we expected everything to happen faster. But looking at other examples of "invent - innovate - implement" phases, 10 years is rather typical. We experienced similar cycles for MEMS getting in consumer products or SOI.
Until recently the major drivers for3D-IC, performance and formfactor, were simply achieveable with conventional scaling and packaging technologies.
Important milestones on the way from university to industry were 3D ITRS roadmaps and engagement from industry funded research. The great production oriented programs like the ones of Sematech, Leti, IMEC or major IDMs are required to mature the technology for HVM and create a support infrastructure.
Each of these milestones could have happened maybe 2 years sooner.
As an equipment manufacturer I could say this delay mainly occured by finding budgets for the tools
Regarding #1
How about processes and solutions for thin wafer handling, and temporary bonding and debonding? Thisis one area identified as still needing viable solutions before market adoption can be achieved. I know you must have some opinions here.The handling of thinned wafers on rigid carriers was first used in volume at compound semiconductor houses and for Si based power devices. In the CMOS world thinning is mainly accomplished with backgrinding tape on large inline systems. We introduced the idea of a rigid carrier for CMOS to enable backside processing on standard equipment.
About 5 years ago we became already experts in bonding and debonding with a variety of different materials (adhesives) - driven by specific customer requirements.
However in no other process technology we learned more about process integration: The challenges did not occur in the bonding and debonding step but rather the process steps inbetween.
The compatibility of the bonded stack had to be proven for each individual customer process flow.
To meet this challenge we decided around 2004:
a) To work closer with one material supplier - Brewer Science. The close cooperation over the past years resulted in new high temperature and high topography capable materials.
b) Focus on process integration: We converted our demo facilities around the world to more independent business units offering process development and pilot line manufacturing. During the process development we can adapt the temporary bond to the customers needs and if required come up with modifications of hardware, software or material. Customers then can run pilot line volume for qualification in a virtual line before investing in equipment.
Today we offer the EVG850 Series Bonders and Debonders as 2 modular platforms for either 200mm or 300mm wafers. Several 300mm equipment sets are already installed worldwide.
A newer focus area is qualification of temporary bonds for subsequent Chip-to-Wafer or Wafer-to-Wafer stacking processes as they occur for example in the EMC-3D process flow http://www.emc3d.org/flow.html
Regarding #3
Paul -
I'm sure you're aware that SUSS MicroTec has promoted their latest bonding and debonding system asbeing configurable to several different material processes that exist in the market, including 3M and TMAT's processes. Can you explain EVG's strategy of working only with one supplier to achieve this?
Our equipment is modular and can be configured to work with a variety of materials. For example we have many users in production with dry laminated adhesive tapes and proprietary spin on adhesives. We still support this - but out of the past years work we recommend the best material / process technology available today from Brewer Science.
So why did we decide to select and focus our efforts?
We were 5 years ago at that stage: A list of materials available, all compatible and qualified on our equipment, but frequently none of them fully compatible to the process integration requirement of our customer.
So we decided to change this by teaming up with Brewer in order to develop new materials for the best process integration. Out of this development customers have access to (in my opinion) the best material solution available today.
The success we had in the last years with bonding / debonding equipment proves this strategy and is a good foundation for future challenges.
Also I firmly believe that discussing the same usually confidential requirement with several (at the end of the day competing) material suppliers is an interesting concept, but could be difficult to maintain in the long run.
Francoise and Paul,
To add to the discussion, I believe that there are (were?) two issues. The first was that the existing solutions were adequate and there was a roadmap for scaling them. The fear factor was low. Secondly, if one had to chose a 3D technology, there were just too many options to pick from, and not enough critical mass around them. This made it difficult to select one option and drive it to HVM.
This is beginning to change. We now need EUV, high k dielectrics, Finfets and low k dielectrics to stay on the scaling roadmap. Introducing one new element in HVM is challenging enough, and the prospect of introducing several simulaneously is daunting. The fear factor is higher and new technology is necessary. In addition, people have thought more about the options and what suits their product offerings best, and the options are being narrowed.
Looking at the discussion thread between both of you, I think of porous low k dielectric development. At SEMATECH, we evaluated several new materials, but the technology started to become real when each tool supplier began providing a material solution to accompany their equipment platform. The EVG-Brewer and Suss-3M collaborations seem very similar. The advantage to the users is that the burden of developing the material-equipment solution now rests with the supplier(s) and they can focus more on the integration.
Discussion Summary
Perhaps a better question is whether 3D IC technology is being delayed at all, or just moving along as historically expected. A 10 year cycle from development to implementation is not unusual in this industry. Paul Lindner of EV Group notes that until recently, major drivers for 3D-IC were achievable with conventional scaling and packaging technologies. Sitram Arkalgud adds to this the many options for 3D integration processes to pick from, and not enough critical mass around them. This made it difficult to select one option and drive it to high volume manufacturing.
Specifically concerning recent collaborative developments in tools and materials processes for temporary bonding and debonding processes, Arkalgud notes that from SEMATECH’s perspective, the advantage to the users is that the burden of developing the material-equipment solution now rests with the supplier(s) and they (users) can focus more on the integration process flow.