How small can we go before we lose control on fab variability?
In pushing toward 22nm node devices we approach the discrete limitations of individual atoms (e.g., barrier layers, dopants, etc.); at what size do we lose control on manufacturing variability regardless of lithographic technology?
I think for straight digital, we have a pretty good runway, although we may start to see fundemental limitations on digital transistor yeild. Anything analog or analog like including memory, is becoming very difficult even at 32-45nm nodes. Adding more transistors seems to be a solution for memories, but that undoes at least some of the shrink savings...if there is any.
In digital, we already hear of transistor matching issues in SRAM arrays limiting yield at 45-32nm nodes. New materials for channels and source/drain may get us around dopant variations, but then lattice mismatch to silicon will probably induce new yield losses. For 22nm node structures, classic control theory and data would suggest a sigma of <1nm, which seems very tough across 300mm wafers.
