Unless the future is only one silicon manufactuer, we will need and have some standards. 3D by its nature calls for integrating pieces built by different fabs. I don't see a scenerio where you could have a Micron building 20 or 30 different footprint and interface memories for 20 or 30 different customers, especially because most of the cusotmers would also want Samsung to do the same as another source. We will break standards ground with standardized 3D memory and eventually extend to a standard 3D bus that can consider power, redundancy, and probably thermal issues.
Assuming that standards refer to chip level standards (a la JEDEC), I agree with Bob. The real power of 3D lies in stacking different technologies (logic, memory, analog, etc) to increase the functionality of the stack and relaizing power and cost reductions and performance benefits. Since very few companies manufacture all these levels themselves, it will be necessary for most 3D stack integrators to source the levels from various manufacturers. Second sourcing will remain an important consideration, so the 3D stack integrator will need the ability to mix and match different manufacturers and this can only come from standardization. Just as JEDEC has a pin-out standard, 3D will require a "via out" standard.
There will also be the need for standardization at the equipment level. The SEMI standards for wafers control a large part of today's manufacturing (edges, bevel, notch, weight, etc) and tools are built according to these standards. The introduction of bonded, edge trimmed and thinned wafers will require modification of these standards.
So will it be more likely that 3D standards evolve as modifications out of SEMI standards, or will there be a set of standards established that are unique to 3D integration?
Stacking heterogenous technologies from various manufacturers at the circuit level will require a "via out" standard. Standardization will likely start with memory and extend to 3D bus. Additionally, current SEMI equipment standards will need to be modified to include bonded, edge-trimmed and thinned wafers.
Unless the future is only one silicon manufactuer, we will need and have some standards. 3D by its nature calls for integrating pieces built by different fabs. I don't see a scenerio where you could have a Micron building 20 or 30 different footprint and interface memories for 20 or 30 different customers, especially because most of the cusotmers would also want Samsung to do the same as another source. We will break standards ground with standardized 3D memory and eventually extend to a standard 3D bus that can consider power, redundancy, and probably thermal issues.
Assuming that standards refer to chip level standards (a la JEDEC), I agree with Bob. The real power of 3D lies in stacking different technologies (logic, memory, analog, etc) to increase the functionality of the stack and relaizing power and cost reductions and performance benefits. Since very few companies manufacture all these levels themselves, it will be necessary for most 3D stack integrators to source the levels from various manufacturers. Second sourcing will remain an important consideration, so the 3D stack integrator will need the ability to mix and match different manufacturers and this can only come from standardization. Just as JEDEC has a pin-out standard, 3D will require a "via out" standard.
There will also be the need for standardization at the equipment level. The SEMI standards for wafers control a large part of today's manufacturing (edges, bevel, notch, weight, etc) and tools are built according to these standards. The introduction of bonded, edge trimmed and thinned wafers will require modification of these standards.
Regarding #2
So will it be more likely that 3D standards evolve as modifications out of SEMI standards, or will there be a set of standards established that are unique to 3D integration?Discussion Summary
Stacking heterogenous technologies from various manufacturers at the circuit level will require a "via out" standard. Standardization will likely start with memory and extend to 3D bus. Additionally, current SEMI equipment standards will need to be modified to include bonded, edge-trimmed and thinned wafers.