Will Extreme Ultraviolet (EUV) lithography ever come to pass? When will nanotube technology hit the market? Will the cost of chips continue to go down? These were just a few of the questions covered during the press lunch at the 2013 Common Platform Technology Forum. The panelists included (seated, left to right): Michael Cadigan, General Manager of IBM’s Microelectronics Division; Gary Patton, VP, IBM’s Semiconductor R&D Center; KH Kim, Executive VP for Samsung Electronics’ Foundry Business; and Mike Noonen, Executive VP of Global Sales and Marketing for GLOBALFOUNDRIES. What follow are excerpts of that discussion.
Question: When will nanotube technology hit the market? Patton: FinFET structures will last a decade, maybe longer. Moving beyond silicon to III-V materials will also help to extend existing designs. (Editor’s note: The III-V compound semiconductors come from combining group III elements (essentially Al, Ga, and In) with group V elements (essentially N, P , As, and Sb) of the periodic table. This results in 12 possible combinations. The most important ones are probably GaAs, InP, GaP, and GaN.) Question: Will EUV ever come to pass? Patton: EUV requires real physics changes. At the recent SEMI Industry Strategy Symposium (ISS), someone said that EUV is hard work. No, it is hard physics. The industry is trying to extend immersion and double patterning, but no one wants to move to quadruple patterning. Question: What does “hard physics” mean? The scientific effort is 20% while the engineering portion is 80%? Patton: I’ve never attached a percentage to it. Perhaps it would be 60% science and 40% engineering effort. Cadigan: We had envisioned the entry point for EUV at the 10-nm-node geometry. Now, that point is 7 nm. If anyone has seen ASML’s EUV tool, they know it’s really tough. Question: If you don’t have EUV at 7 nm, will you need triple or quad patterning? Cadigan: Yes, we always have an alternative. For example, fully depleted (FD) silicon-on-insulator (FD-SOI) was ready at about the same time as FinFET technology. If FinFET had been late, FD-SOI was the backup plan. Question: Costs continue to rise for chip design and manufacturing. Will Moore’s Law end soon? Noonen: Cost is where the rubber meets the road. Fabs must make money, but need to offer designers the right mix of power, performance, and cost (i.e., they must right-size to the right solutions). This goes beyond one metric, beyond a geometry. Question: Lowering the cost of chips is a maturation of process. Is that maturation taking more time? Noonen: We are working on 28-nm to 14-nm geometries all at once, accelerating the process to bring forth multiple nodes. This is breaking the typical two-year duty cycle between nodes from previous years. Cadigan: I use the phrase time-to-market (TTM) instead of maturation. Our partners want earlier involvement to bring their technology to market at a faster pace. The model is shifting in 2013 – we all must work faster. For us (IBM), that shift means moving more quickly from the Albany facility to Fishkill to our customers to shorten the time for development – and hence TTM. Science is nice, but cost is critical. We need to drive the cost out of the technology. For example, we are leveraging what we learn in Fishkill – which is not high-volume – along with Globalfoundries and Samsung to leverage the total cost point. Question: Will 450-mm wafers be available in the latter part of this decade? Cadigan: The Global G450 Consortium now has a consensus that 450 mm is happening. But I don’t know the timing of 450 mm. Volume production will probably come at the end of the decade. The challenge is that the timing of 450-mm wafers will depend upon lithography technology – back to the EUV question. But EUV will come to market for both 300 mm and 450 mm (see “CNSE Readying NFX Fab for G450C, EUV Efforts”). Question: Will the tools at 10 nm reduce the need for triple and quadruple patterning? Patton: We’ve extended immersion for a long time. Programmable light-source work is ongoing with ASML. Directed self-assembly (DSA) could be used to avoid quadruple (4) patterning. Question: Broadcom’s CEO is quoted as saying that the benefits for cost on scaling will not continue. Cost benefits of scaling have gone away. Do you agree? Patton: Comparisons between 20-nm to 14-nm nodes are not good, since those are not full nodes. You need to compare cost scaling between full nodes. In the past, 50% scaling provided 20% cost savings. Those ratios will change. Question: The original idea of the Common Platform Alliance was to share fabs. Is that still possible? Cadigan: That was the original idea – release a design into two different fabs using the same kits (PDKs). As we evolved, we realized that only a few companies would do that. Samsung will tune its process slightly off of our common platform base. Or Globalfoundries will have one or two large clients who want a tuning. Our goal is still common-based foundational content. Now, it’s okay to personalize it. That’s why we are doing more in Albany instead of Fishkill.
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Semiconductor Leaders Respond at Common Platform Technology Q&A
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