Agenda

Date and TimeTitle
May 7, 2020
8:11am - 9:11am (Pacific)
Sample Session Two

Sessions can be used to serve on-demand or live webcast and webinars to your attendees. Select the time of your event, and then specify whether you will be hosting a live or on-demand event. Turn on the desired sections of your Interaction Panel to encourage conversation among attendees.

May 25, 2020
10:30am - 1:30pm (Tallinn)
Monday 25May rehearsal
May 25, 2020
12:10pm - 1:10pm (Tallinn)
Test live stream Uljana
May 25, 2020
12:20pm - 1:20pm (Tallinn)
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May 25, 2020
2:00pm - 3:00pm (Berlin)
Opening - Welcome to Virtual ETS 2020
May 25, 2020
4:00pm - 6:00pm (Tallinn)
Keynote 1: Resilience of AI-driven Applications

Ravishankar K. Iyer, George and Ann Fisher Distinguished Professor of Engineering at the University of Illinois at Urbana-Champaign, USA

The emerging innovations in computer science and engineering are likely to come from “AI-systems” that seamlessly augment human capabilities and optimally interact with other manmade and natural systems with a focus on seamless availability of dynamic decision-making capabilities. Applications, such as, autonomous vehicles, robotic management and control, high performance computing, all driven by advanced data-analytics and artificial intelligence algorithms, have spawned a level of complexity where traditional fault-tolerance methods cannot form the backbone for resilient system design. Driven by observations of operational failures of autonomous vehicles, surgical robots, and extreme-scale computing systems as examples, this talk will present directions of research that leverage probabilistic graphical models (PGMs) for building and validating a new generation of resilient and safety-critical applications.

May. 25, 2020 - 7:00 pm to Jun. 01, 2020 - 7:00 pm (Tallinn)ETS 2020 Proceedings

The proceedings of the 25th European Test Symposium are available at the following address (external link):

ETS 2020 Proceedings (a shared OwnCloud folder)

Password: WhiteNightsinTallinn2020

May. 25, 2020 - 7:30 pm to Jun. 01, 2020 - 7:30 pm (Tallinn)[L1.1] Test Sequence-Optimized BIST for Automotive Applications

Authors: Jerzy TYSZER (Poznan University of Technology), Grzegorz MRUGALSKI, Nilanjan MUKHERJEE, Janusz RAJSKI, Łukasz RYBAK (Mentor, A Siemens Business)

Test Sequence-Optimized BIST for Automotive Applications

Keywords: embedded-test, logic built-in self-test, LFSR reseeding, scan-based testing, test application time

May. 25, 2020 - 8:00 pm to Jun. 01, 2020 - 8:00 pm (Tallinn)[L1.2] Dynamic Authentication-Based Secure Access to Test Infrastructure

Authors: Michele PORTOLAN, Vincent REYNAUD (Grenoble-INP), Paolo MAISTRI (CNRS), Regis LEVEUGLE (Grenoble INP)

Dynamic Authentication-Based Secure Access to Test Infrastructure

Keywords: Reconfigurable Scan Networks, Secure Access, Authentication, Automated Test Environments, IEEE 1687

May. 25, 2020 - 8:30 pm to Jun. 01, 2020 - 8:30 pm (Tallinn)[L1.3] Minimal Witnesses for Security Weaknesses in Reconfigurable Scan Networks

Authors: Pascal RAIOLA, Tobias PAXIAN, Bernd BECKER (University of Freiburg)

Minimal Witnesses for Security Weaknesses in Reconfigurable Scan Networks

Keywords: Reconfigurable Scan Network, Hardware Security, Data Dependency, IEEE Std 1687, Insecure Data Flow

May. 25, 2020 - 9:00 pm to Jun. 01, 2020 - 9:00 pm (Tallinn)[L2.1] Testing Scouting Logic-Based Computation-in-Memory Architectures

Authors: Moritz FIEBACK, Surya NAGARAJAN, Rajendra BISHNOI (Delft University of Technology), Mehdi TAHOORI (Karlsruhe Institute of Technology), Mottaqiallah TAOUIL, Said HAMDIOUI (Delft University of Technology)

Testing Scouting Logic-Based Computation-in-Memory Architectures

Keywords: test, computation-in-memory (CIM), in-memory computing, emerging memories, RRAM

May. 25, 2020 - 9:30 pm to Jun. 01, 2020 - 9:30 pm (Tallinn)[L2.2] Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory

Authors: Sarath MOHANACHANDRAN NAIR, Christopher MÜNCH, Mehdi TAHOORI (Karlsruhe Institute of Technology)

Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory

Keywords: STT-MRAM, In-memory computing, Defect modeling

May. 25, 2020 - 10:00 pm to Jun. 01, 2020 - 10:00 pm (Tallinn)[L2.3] MBIST Support for Reliable eMRAM Sensing

Authors: Jongsin YUN, Benoit NADEAU-DOSTIE, Martin KEIM (Mentor, A Siemens Business), Cyrille DRAY, Mehdi BOUJAMAA (ARM)

MBIST Support for Reliable eMRAM Sensing

Keywords: eMRAM, yield, trim, reference, read operation

May. 25, 2020 - 10:30 pm to Jun. 01, 2020 - 10:30 pm (Tallinn)[L3.1] Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching Weakest Faults

Authors: Min-Chun HU (National Tsing-Hua University), Zhan GAO (IMEC), Santosh MALAGI, Joe SWENTON (Cadence Design Systems), Jos HUISKEN, Kees GOOSSENS (Eindhoven University of Technology), Cheng-Wen WU (National Tsing Hua University), Erik Jan MARINISSEN (IMEC)

Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching Weakest Faults

Keywords: cell-aware test, weak fault, hard fault, defect characterization, ATPG

May. 25, 2020 - 11:00 pm to Jun. 01, 2020 - 11:00 pm (Tallinn)[L3.2] Variation-Aware Defect Characterization at Cell Level

Authors: Zahra NAJAFI HAGHI, Marzieh HASHEMIPOUR NAZARI, Hans-Joachim WUNDERLICH (Stuttgart University)

Variation-Aware Defect Characterization at Cell Level

Keywords: Small delay faults, variations, reliability, defect modeling, statistical learning

May. 25, 2020 - 11:30 pm to Jun. 01, 2020 - 11:30 pm (Tallinn)[L3.3] Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model

Authors: Ching-Yuan CHEN (Duke University), Ching-Hung CHENG, Jiun-Lang HUANG (National Taiwan University), Krishnendu CHAKRABARTY (Duke University)

Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model

Keywords: functional-like, automatic test pattern generation, full-scan

May 26, 2020
5:00am - 7:00am (Tallinn)
Keynote 2: Safety-Critical Applications: An EDA perspective

Alessandra Nardi, Software Engineering Group Director, Cadence Design Systems, USA

The latest technology advancements, such as 5G and machine learning, are enabling an increasing number of safety-critical applications, which are becoming more and more pervasive industry segments like autonomous vehicles, avionics, medical, and robotics. This talk takes a look from an EDA perspective at the challenges and the opportunities introduced by safety-critical applications, focusing specifically on functional safety requirements.

May 26, 2020
8:00am - 9:00am (Helsinki)
Session L5 - Technology: Thermal Neutrons: a Possible Threat for Supercomputers and Safety Critical Applications

Daniel OLIVEIRA (UFPR), Sean BLANCHARD, Nathan DEBARDELEBEN (LANL), Fernando SANTOS, Gabriel DAVILA, Philippe NAVAUX (UFRGS), Cazzaniga CARLO (Rutherford Appleton Laboratory-ISIS), Christopher FROST (STFC), Paolo RECH (LANL).

Keywords: Radiation test, Thermal Neutrons, Reliability

Paper 63: Thermal Neutrons: a Possible Threat for Supercomputers and Safety Critical Applications

May 26, 2020
8:00am - 9:00am (Tallinn)
A Built-In Self-Test Method For MEMS Piezoresistive Sensor

Manhong ZHU, Jia LI, Weibing WANG, Dapeng CHEN (Institute of Microelectronics, Chinese Academy of Sciences)

Keywords: MEMS; piezoresistive sensor; built-in self-test; electric excitation

Paper 35: A Built-In Self-Test Method For MEMS Piezoresistive Sensor

May 26, 2020
8:00am - 9:00am (Tallinn)
Session L5 - Technology: Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios
May 26, 2020
10:00am - 11:00am (Tallinn)
Testing Scouting Logic-Based Computation-in-Memory Architectures

Moritz FIEBACK, Surya NAGARAJAN, Rajendra BISHNOI (Delft University of Technology), Mehdi TAHOORI (Karlsruhe Institute of Technology), Mottaqiallah TAOUIL, Said HAMDIOUI (Delft University of Technology)

Keywords: test, computation-in-memory (CIM), in-memory computing, emerging memories, RRAM

Paper 76: Testing Scouting Logic-Based Computation-in-Memory Architectures

May. 26, 2020 - 12:00 pm to Jun. 02, 2020 - 12:00 pm (Tallinn)[L4.1] Nonlinear Codes for Control Flow Checking

Authors: Giorgio DI NATALE (TIMA), Osnat KEREN (Bar-Ilan University)

Nonlinear Codes for Control Flow Checking

Keywords: CFC

May. 26, 2020 - 12:30 pm to Jun. 02, 2020 - 12:30 pm (Tallinn)[L4.2] QAMR: an Approximation-Based FullyReliable TMR Alternative for Area Overhead Reduction

Authors: Bastien DEVEAUTOUR, Marcello TRAIOLA, Arnaud VIRAZEL, Patrick GIRARD (LIRMM)

QAMR: an Approximation-Based FullyReliable TMR Alternative for Area Overhead Reduction

Keywords: Combinational circuits; fault tolerance; error correction; triple modular redundancy; approximate computing

May 26, 2020
1:00pm - 2:00pm (Tallinn)
Analog Fault Simulation - a Hot Topic!

Moderators: Lorena ANGHEL - TIMA, FR and Gildas LEGER - IMSE-CNM, ES

103 Analog Fault Simulation - a Hot Topic!
  Stephen SUNTER (Mentor, A Siemens Business)
  Keywords: Analog defect simulation, fault modeling

May. 26, 2020 - 1:00 pm to Jun. 02, 2020 - 1:00 pm (Tallinn)[L4.3] Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs

Authors: Felipe AUGUSTO DA SILVA, Ahmet Cagri BAGBABA (Cadence Design Systems GmbH), Sandro SARTONI, Riccardo CANTORO, Matteo SONZA REORDA (Politecnico di Torino), Said HAMDIOUI (Delft University of Technology), Christian SAUER (Cadence Design Systems GmbH)

Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs

Keywords: ISO26262; Safe Faults; Fault Injection; Formal Methods; Simulation; Functional Safety; Verification

May. 26, 2020 - 1:30 pm to Jun. 02, 2020 - 1:30 pm (Tallinn)[L5.1] Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios

Authors: Michele STUCCHI, Ferenc FODOR, Erik Jan MARINISSEN (IMEC)

Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios

Keywords: resistance, vertical interconnect, cross-bridge Kelvin resistor, current and voltage distributions

May. 26, 2020 - 2:00 pm to Jun. 02, 2020 - 2:00 pm (Tallinn)[L5.2] A Built-In Self-Test Method For MEMS Piezoresistive Sensor

Authors: Manhong ZHU, Jia LI, Weibing WANG, Dapeng CHEN (Institute of Microelectronics, Chinese Academy of Sciences)

A Built-In Self-Test Method For MEMS Piezoresistive Sensor

Keywords: MEMS; piezoresistive sensor; built-in self-test; electric excitation

May. 26, 2020 - 2:30 pm to Jun. 02, 2020 - 2:30 pm (Tallinn)[L5.3] Thermal Neutrons: a Possible Threat for Supercomputers and Safety Critical Applications

Authors: Daniel OLIVEIRA (UFPR), Sean BLANCHARD, Nathan DEBARDELEBEN (LANL), Fernando SANTOS, Gabriel DAVILA, Philippe NAVAUX (UFRGS), Cazzaniga CARLO (Rutherford Appleton Laboratory-ISIS), Christopher FROST (STFC), Paolo RECH (LANL)

Thermal Neutrons: a Possible Threat for Supercomputers and Safety Critical Applications

Keywords: Radiation test, Thermal Neutrons, Reliability

May. 26, 2020 - 3:00 pm to Jun. 02, 2020 - 3:00 pm (Tallinn)[L6.1] Latent Defect Screening with Visually-Enhanced Dynamic Part Average Testing

Authors: Anthony COYETTE, Wim DOBBELAERE, Ronny VANHOOREN (ON Semiconductor), Nektar XAMA (KULeuven), Jhon GOMEZ, Georges GIELEN (KU Leuven)

Latent Defect Screening with Visually-Enhanced Dynamic Part Average Testing

Keywords: Latent defects, outlier detection, analog and mixed-signal testing, integrated circuits, DPAT, visualization

May. 26, 2020 - 3:30 pm to Jun. 02, 2020 - 3:30 pm (Tallinn)[L6.2] PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques

Authors: Katherine Shu-Min LI (National Sun Yat-sen University), Peter Yi-Yu LIAO, Leon CHOU, Ken Chau-Cheung CHENG, Andrew Yi-Ann HUANG (NXP Semiconductor Taiwan Ltd.), Sying-Jyan WANG, Gus Chang-Hung HAN (National Chung-Hsing University)

PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques

Keywords: wafermap, defect pattern, yield learning, clustering, machine learning

May. 26, 2020 - 4:00 pm to Jun. 02, 2020 - 4:00 pm (Tallinn)[L6.3] Avoiding Mixed-Signal Field Returns by Outlier Detection of Hard-to-Detect Defects based on Multivariate Statistics

Authors: Nektar XAMA, Jakob RAYMAEKERS (KU Leuven), Martin ANDRAUD (Aalto university), Jhon GOMEZ (KU Leuven), Wim DOBBELAERE, Ronny VANHOOREN, Anthony COYETTE (ON Semiconductor), Georges GIELEN (KU Leuven)

Avoiding Mixed-Signal Field Returns by Outlier Detection of Hard-to-Detect Defects based on Multivariate Statistics

Keywords: analog and mixed-signal test, test escape screening, multivariate statistics, latent defect testing

May. 26, 2020 - 4:30 pm to Jun. 02, 2020 - 4:30 pm (Tallinn)[L7.1] The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs

Authors: David KNICHEL (Ruhr-University Bochum), Thorben MOOS (Ruhr-University Bochum, Horst Görtz Institute for IT Security), Amir MORADI (Ruhr-University Bochum), Amir MORADI (RUB)

The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs

Keywords: hardware Trojan, ASIC, side-channel analysis, time-to-digital converter

May. 26, 2020 - 5:00 pm to Jun. 02, 2020 - 5:00 pm (Tallinn)[L7.2] Modeling Static Noise Margin for FinFET based SRAM PUFs

Authors: Shayesteh MASOUMIAN, Georgios SELIMIS, Roel MAES, Geert-Jan SCHRIJEN (Intrinsic ID), Said HAMDIOUI, Mottaqiallah TAOUIL (Delft University of Technology)

Modeling Static Noise Margin for FinFET based SRAM PUFs

Keywords: SRAM PUF, FinFET, Static noise margin, process variation, temperature

May. 26, 2020 - 5:30 pm to Jun. 02, 2020 - 5:30 pm (Tallinn)[L7.3] Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism

Authors: Mohamed ELSHAMY (Sorbonne Univ., CNRS, LIP6), Giorgio DI NATALE (TIMA), Antonios PAVLIDIS (Sorbonne Univ., CNRS, LIP6), Marie-Minerve LOUERAT (Sorbonne Univ., CNRS), Haralampos STRATIGOPOULOS (Sorbonne Univ., CNRS, LIP6)

Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism

Keywords: Hardware Security, Hardware Trojans, Analog and Mixed-Signal Circuits, Test Access Mechanism

May. 26, 2020 - 6:00 pm to Jun. 02, 2020 - 6:00 pm (Tallinn)[L8.1] LiD-CAT: A Lightweight Detector for Cache ATtacks

Authors: Cezar Rodolfo WEDIG REINBRECHT, Said HAMDIOUI, Mottaqiallah TAOUIL (Delft University of Technology), Behrad NIAZMAND, Tara GHASEMPOURI, Jaan RAIK (Tallinn University of Technology), Johanna SEPULVEDA (Airbus Defence and Space)

LiD-CAT: A Lightweight Detector for Cache ATtacks

Keywords: cache attacks, security properties, lightweight detector

May. 26, 2020 - 6:30 pm to Jun. 02, 2020 - 6:30 pm (Tallinn)[L8.2] Built-In Predictors for Dynamic Crosstalk Avoidance

Authors: Rezgar SADEGHI, Zainalabedin NAVABI (University of Tehran)

Built-In Predictors for Dynamic Crosstalk Avoidance

Keywords: Crosstalk Fault, Interconnect, Communication Bus, Crosstalk Prediction, Crosstalk Model

May. 26, 2020 - 7:00 pm to Jun. 02, 2020 - 7:00 pm (Tallinn)[L8.3] A New Monitor Insertion Algorithm for Intermittent Fault Detection

Authors: Hassan EBRAHIMI, Hans KERKHOFF (University of Twente)

A New Monitor Insertion Algorithm for Intermittent Fault Detection

Keywords: Reliability; No Faults Found, Intermittent Resistive Faults, Intermittent Fault Detection

May. 27, 2020 - 6:00 am to Jun. 16, 2020 - 6:00 am (Tallinn)[ET.1] Analog Fault Simulation - a Hot Topic!

Authors: Stephen SUNTER (Mentor, A Siemens Business)

Analog Fault Simulation - a Hot Topic!

Keywords: Analog defect simulation, fault modeling

May. 27, 2020 - 12:00 pm to Jun. 03, 2020 - 12:00 pm (Tallinn)[S1.1] On-chip reduced-code static linearity test of Vcm-based switching SAR ADCs using an incremental analog-to-digital converter

Authors: Renato FEITOZA, Manuel BARRAGAN (TIMA Laboratory), Antonio GINES (IMSE-CNM (CSIC, Universidad de Sevilla)), Salvador MIR (TIMA Laboratory)

On-chip reduced-code static linearity test of Vcm-based switching SAR ADCs using an incremental analog-to-digital converter

Keywords: ADC BIST; Static linearity test; Reduced-code test

May. 27, 2020 - 12:30 pm to Jun. 03, 2020 - 12:30 pm (Tallinn)[S1.2] Digital Defect Based Built-in Self-Test for Low Dropout Voltage Regulators

Authors: Mehmet INCE (Arizona State University)

Digital Defect Based Built-in Self-Test for Low Dropout Voltage Regulators

Keywords: Built-in Self-Test, LDO

May. 27, 2020 - 1:00 pm to Jun. 03, 2020 - 1:00 pm (Tallinn)[S1.3] Monitoring of BTI and HCI Aging in SRAM Decoders

Authors: Helen-Maria DOUNAVI, Yiorgos TSIATOUHAS (Univ. of Ioannina)

Monitoring of BTI and HCI Aging in SRAM Decoders

Keywords: BTI, HCI, aging monitoring, SRAM Decoders, transistor aging, reliability, failure prediction

May. 27, 2020 - 1:30 pm to Jun. 03, 2020 - 1:30 pm (Tallinn)[S1.4] G-PUF: An Intrinsic PUF Based on GPU Error Signatures

Authors: Bruno FORLIN, Ronaldo HUSEMANN, Luigi CARRO (UFRGS), Cezar Rodolfo WEDIG REINBRECHT, Said HAMDIOUI, Mottaqiallah TAOUIL (Delft University of Technology)

G-PUF: An Intrinsic PUF Based on GPU Error Signatures

Keywords: G-PUF, Physically Unclonable Functions, GPU, Security, Intrinsic PUF

May. 27, 2020 - 2:00 pm to Jun. 03, 2020 - 2:00 pm (Tallinn)[S1.5] A SIFT-based Waveform Clustering Method for aiding analog/mixed-signal IC Verification

Authors: Andrei GAITA, Georgian NICOLAE (Universitatea Politehnica din Bucuresti), Emilian Constantin DAVID (Infineon Technologies Bucharest, Romania), Andi BUZO (Infineon), Georg PELZ (Infineon Technologies, Neubiberg, Germany)

A SIFT-based Waveform Clustering Method for aiding analog/mixed-signal IC Verification

Keywords: SIFT, wavelet, DCT, K-means

May. 27, 2020 - 2:30 pm to Jun. 03, 2020 - 2:30 pm (Tallinn)[S1.6] Learning-Based Cell-Aware Defect Diagnosis of Customer Returns

Authors: Safa MHAMDI, Patrick GIRARD, ARNAUD VIRAZEL (LIRMM), ALBERTO BOSIO (Lyon Institute of Nanotechnology), Aymen LADHAR (STM)

Learning-Based Cell-Aware Defect Diagnosis of Customer Returns

Keywords: Diagnosis, Customer Returns, Machine Learning

May. 27, 2020 - 3:00 pm to Jun. 03, 2020 - 3:00 pm (Tallinn)[S2.1] Anomaly Detection in Embedded Systems Using Power and Memory Side Channels

Authors: Jiho PARK, Virinchi Roy SURABHI, Prashanth KRISHNAMURTHY, Siddharth GARG, Ramesh KARRI, Farshad KHORRAMI (NYU)

Anomaly Detection in Embedded Systems Using Power and Memory Side Channels

Keywords: Anomaly detection, cyber security, power consumption, memory access, one-class support vector machine

May. 27, 2020 - 3:30 pm to Jun. 03, 2020 - 3:30 pm (Tallinn)[S2.2] Automated Graph-Based Fault Injection Into Virtual Prototypes for Robustness Evaluation

Authors: Jo LAUFENBERG, Thomas KROPF, Oliver BRINGMANN (University of Tuebingen)

Automated Graph-Based Fault Injection Into Virtual Prototypes for Robustness Evaluation

Keywords: fault injection, graph, robustness, simulation, virtual prototype

May. 27, 2020 - 4:00 pm to Jun. 03, 2020 - 4:00 pm (Tallinn)[S2.3] Efficient Prognostication of Pattern Count with Different Input Compression Ratios

Authors: Fong-Jyun TSAI, Chong-Siao YE (National Cheng Kung University), Yu HUANG (Mentor, A Siemens Business), Kuen Jong LEE (National Cheng Kung Univ), Wu-Tung CHENG (Mentor, A Siemens Business), Sudhakar REDDY (University of Iowa), Mark KASSAB , Janusz RAJSKI (Mentor, A Siemens Business)

Efficient Prognostication of Pattern Count with Different Input Compression Ratios

Keywords: design for testability, embedded-test, scan-based designs, runtime reduction

May. 27, 2020 - 4:30 pm to Jun. 03, 2020 - 4:30 pm (Tallinn)[S2.4] Failure and Attack Detection by Digital Sensors

Authors: Md Toufiq Hasan ANIK, Rachit SAINI (University of Maryland Baltimore County), Jean-Luc DANGER (Télécom Paris, Institut Polytechnique de Paris), Sylvain GUILLEY (Télécom ParisTech, Université Paris-Saclay), Naghmeh KARIMI (University of Maryland Baltimore County)

Failure and Attack Detection by Digital Sensors

Keywords: Digital Sensors, Failure Detection, Attack Detection, Security, Aging

May. 27, 2020 - 5:00 pm to Jun. 03, 2020 - 5:00 pm (Tallinn)[S2.5] Detection of Rowhammer Attacks in SoCs with FPGAs

Authors: Rana ELNAGGAR, Siyuan CHEN (Duke University), Peilin SONG (IBM Corp.), Krishnendu CHAKRABARTY (Duke University)

Detection of Rowhammer Attacks in SoCs with FPGAs

Keywords: FPGA-SoC, Rowhammer, security, FPGA-to-microprocessor SDRAM

May. 27, 2020 - 5:30 pm to Jun. 03, 2020 - 5:30 pm (Tallinn)[S2.6] IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks

Authors: Erik LARSSON, Zehang XIANG, Prathamesh MURALI (Lund University)

IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks

Keywords: IEEE Std. P1687.1, IEEE Std. 1687, test, localization, repair, access control

May. 27, 2020 - 6:00 pm to Jun. 03, 2020 - 6:00 pm (Tallinn)[CS.1] Enabling DFT and Fast Silicon Bring-up for Massive AI Chip – Case Study

Authors: 2020-05-27 18:00

[CS.1] Enabling DFT and Fast Silicon Bring-up for Massive AI Chip – Case Study

2020-06-03 18:00

May. 27, 2020 - 6:30 pm to Jun. 03, 2020 - 6:30 pm (Tallinn)[CS.2] IEEE 1687-Based Testing Methodology for AI SoC Integrating Embedded TAP and IEEE 1500 Interfaces

Authors: 2020-05-27 18:30

[CS.2] IEEE 1687-Based Testing Methodology for AI SoC Integrating Embedded TAP and IEEE 1500 Interfaces

2020-06-03 18:30

May. 28, 2020 - 6:00 am to Jun. 17, 2020 - 6:00 am (Tallinn)[ET.2] Device-Aware Test for Emerging Memories: Enabling your test program for DPPB level

Authors: Said HAMDIOUI (Delft University of Technology)

Device-Aware Test for Emerging Memories: Enabling your test program for DPPB level

Keywords: Device-Aware Test, STT-MRAM testing, RRAM testing, Defect modeling, Fault Modeling, Test generation

May 28, 2020
8:00am - 9:00am (Tallinn)
(SP) Session S1 - Solutions towards the technology layer - Learning-Based Cell-Aware Defect Diagnosis of Customer Returns

Safa MHAMDI, Patrick GIRARD, ARNAUD VIRAZEL (LIRMM), ALBERTO BOSIO (Lyon Institute of Nanotechnology), Aymen LADHAR (STM)

Keywords: Diagnosis, Customer Returns, Machine Learning

Poster: Learning-Based Cell-Aware Defect Diagnosis of Customer Returns

Paper 36: Learning-Based Cell-Aware Defect Diagnosis of Customer Returns

May. 28, 2020 - 12:00 pm to Jun. 04, 2020 - 12:00 pm (Tallinn)[SS.1.1] Design Obfuscation versus Test
May. 28, 2020 - 12:30 pm to Jun. 04, 2020 - 12:30 pm (Tallinn)[SS.1.2] Logic Locking: Metrics, Secure Implementation and Connections to VLSI Test Concepts
May. 28, 2020 - 1:00 pm to Jun. 04, 2020 - 1:00 pm (Tallinn)[SS.1.3] Secure High-level Synthesis for Hardware Obfuscation
May. 28, 2020 - 1:30 pm to Jun. 04, 2020 - 1:30 pm (Tallinn)[SS.2.1] A Path Toward Realizing the Vision of System-Board-Chip Test Synergy
May. 28, 2020 - 2:00 pm to Jun. 04, 2020 - 2:00 pm (Tallinn)[SS.2.2] Linking Chip, Board, and System Test via Standards, IEEE P1687.1
May. 28, 2020 - 2:30 pm to Jun. 04, 2020 - 2:30 pm (Tallinn)[SS.2.3] Linking Chip, Board, and System Test via Standards, What a P1687.1 Tool would look like?
May. 28, 2020 - 3:00 pm to Jun. 04, 2020 - 3:00 pm (Tallinn)[SS.3.1] PUFs Introduction and Standardization Process
May. 28, 2020 - 3:30 pm to Jun. 04, 2020 - 3:30 pm (Tallinn)[SS.3.2] Leveraging Secure IC Testing for Secure PUF Enrollment
May. 28, 2020 - 4:00 pm to Jun. 04, 2020 - 4:00 pm (Tallinn)[SS.3.3] Deep Learning Techniques for Challenge/Response Pair Database Management During the Life Cycle
May. 28, 2020 - 4:30 pm to Jun. 04, 2020 - 4:30 pm (Tallinn)[SS.3.4] Enhancing the PUF Integrity and Security in Mission Mode
May. 28, 2020 - 5:30 pm to Jun. 04, 2020 - 5:30 pm (Tallinn)[SS.4.2] R3AI: Hardware Design Principles for Real-Time, Resource-Savvy, and Risk-Aware AI
May. 28, 2020 - 6:00 pm to Jun. 04, 2020 - 6:00 pm (Tallinn)[SS.4.3] On Adversarial Susceptibility and Defense of Neural Networks
May. 28, 2020 - 6:30 pm to Jun. 04, 2020 - 6:30 pm (Tallinn)[SS.4.4] Reliable Intelligence in Unreliable Environment
May. 29, 2020 - 6:00 am to Jun. 18, 2020 - 6:00 am (Tallinn)[ET.3] Design, Verification, Test and In-Field Implications of Approximate Computing Systems

Authors: Stefano DI CARLO, Alessandro SAVINO (Politecnico di Torino), Marcello TRAIOLA, Patrick GIRARD, ARNAUD VIRAZEL (LIRMM), Vasicek ZDENEK (Brno University of Technology)

Design, Verification, Test and In-Field Implications of Approximate Computing Systems

Keywords: Approximate computing, energy efficiency, testing, verification, design space exploration, reliability

May. 29, 2020 - 12:00 pm to Jun. 05, 2020 - 12:00 pm (Tallinn)[PF.1] Evaluation of Deep Neural Networks reliability according to their data type representation

Authors: Annachiara RUOSPO (Politecnico di Torino)

Evaluation of Deep Neural Networks reliability according to their data type representation

Keywords: Deep Learning, Test, Reliability, Fault Injection, Safety, Automotive

May. 29, 2020 - 12:30 pm to Jun. 05, 2020 - 12:30 pm (Tallinn)[PF.2] Two-Layer Lightweight Secure HW-Based Accelerator for AUTOSAR Communication Module

Authors: Ahmed HAMED (Mentor, a Siemens Business), Mona SAFAR, El-Kharashi M. WATHEQ (Ain Shams University), Ashraf SALEM (Mentor, a Siemens Business)

Two-Layer Lightweight Secure HW-Based Accelerator for AUTOSAR Communication Module

Keywords: AUTOSAR, COM ASIP, AUTOSAR Com IPDUs, AUTOSAR Com Signals, ECU

May. 29, 2020 - 1:00 pm to Jun. 05, 2020 - 1:00 pm (Tallinn)[PF.3] Development of a portable Software Test Library in C language

Authors: Davide PIUMATTI (Politecnico di Torino)

Development of a portable Software Test Library in C language

Keywords: Software Test Library, Testing, Microcontroller, Safaty-Critical Application

May. 29, 2020 - 1:30 pm to Jun. 05, 2020 - 1:30 pm (Tallinn)[PF.4] Design, Analysis and Implementation of Physically Unclonable Function based Authentication Frameworks for Internet-of-Things

Authors: Urbi CHATTERJEE (Indian Institute of Technology Kharagpur)

Design, Analysis and Implementation of Physically Unclonable Function based Authentication Frameworks for Internet-of-Things

Keywords: Physically Unclonable Functions, Authentication, Key management, Cryptographic Protocols, Anonymity

May. 29, 2020 - 2:00 pm to Jun. 05, 2020 - 2:00 pm (Tallinn)[PF.5] Silicon Demonstration of a Hardware Ransomware

Authors: Felipe ALMEIDA

Silicon Demonstration of a Hardware Ransomware

May. 29, 2020 - 2:30 pm to Jun. 05, 2020 - 2:30 pm (Tallinn)[PA.1] Pattern Analysis for Power Safe Testing and Prediction Using Machine Learning

Authors: Harshad DHOTRE

Pattern Analysis for Power Safe Testing and Prediction Using Machine Learning

Keywords: DFT, Low power ATPG, Pattern Re-targeting, Machine learning, Clustering, Prediction, IR-drop

May. 29, 2020 - 3:00 pm to Jun. 05, 2020 - 3:00 pm (Tallinn)[PA.2] Contact related Failure Detection of Semiconductor Layer Stacks using an Acoustic Emission Test Method

Authors: Marianne UNTERREITMEIER, Oliver NAGLER

Contact related Failure Detection of Semiconductor Layer Stacks using an Acoustic Emission Test Method

Keywords: wafer test, probing, semiconductor, cracks, acoustic emission, indenter

May. 29, 2020 - 3:30 pm to Jun. 05, 2020 - 3:30 pm (Tallinn)[PA.3] Test Techniques for Approximate Digital Circuits

Authors: Marcello TRAIOLA, Arnaud VIRAZEL, Patrick GIRARD, ALBERTO BOSIO

Test Techniques for Approximate Digital Circuits

Keywords: Approximate Computing, Testing, Integrated Circuits

May. 29, 2020 - 4:00 pm to Jun. 05, 2020 - 4:00 pm (Tallinn)[PA.4] Digital Design Techniques for Dependable High Performance Computing

Authors: Sarah AZIMI

Digital Design Techniques for Dependable High Performance Computing

Keywords: High-performance Computing, Modern VLSI Technologies, Radiation Effects, Reliability

May. 29, 2020 - 4:30 pm to Jun. 05, 2020 - 4:30 pm (Tallinn)[PA.5] Novel Hardware Verification Methods for FPGAs

Authors: Alexandra KOURFALI, Dirk STROOBANDT

Novel Hardware Verification Methods for FPGAs

Keywords: FPGA, testing, verification, debugging, fault tolerance, fault injection, parameterized configuration

May. 29, 2020 - 5:00 pm to Jun. 05, 2020 - 5:00 pm (Tallinn)[PA.6] Optimization of Cell-Aware Test

Authors: Zhan GAO

Optimization of Cell-Aware Test

Keywords: cell-aware test, defect detection matrix, weak fault, defect characterization, ATPG

May. 29, 2020 - 5:30 pm to Jun. 05, 2020 - 5:30 pm (Tallinn)[PA.7] Memory Reliability Analysis Framework: Modelling and Mitigation

Authors: Daniel KRAAK

Memory Reliability Analysis Framework: Modelling and Mitigation

Keywords: SRAM, Reliability, Aging, PVT, Mitigation

Jun 1, 2020
6:00pm - 7:00pm (Tallinn)
Bonus Session - Virtual Social Event
Warning! The following presentation has not passed peer review.
 
Since this is a testing conference, please be sure to verify any of the claims in this virtual tour of Tallinn.
 
Abstract
 
Hearing regrets from many colleagues who were looking forward to come to Tallinn in person this Spring, we decided to run a virtual Social Event for you - at least the city tour part of it. As a result, we spent this weekend having a lot of fun in town ;) Some moments have been recorded and composed into a short movie.
 
By filming this movie we were trying to show our respect and appreciation to ALL THE AUTHORS who had to record their slide show presentations for ETS'2020. We recognize this hard work that often requires many trials and errors!
 
In order to fully stand in the ETS'2020 authors' shoes, we limited the video duration by the size of a standard presentation slot. A lot of content had to be squeezed into such a tiny time slot. We had to rely on many tricks as well as carefull content selection to be able to accomplish this challenge (there is still a lot to see in Tallinn, and a lot of actually filmed content, which is not included into the movie). 

Enjoy! ;)

Jun 1, 2020
7:00pm - 8:00pm (Tallinn)
Closing - Virtual ETS 2020