With separate 2D roadmaps already needed for Logic, DRAM, and Flash, will divergent IC applications call for multiple 3D roadmaps (perhaps global vs. local interconnect, memory-stack vs. SoC, etc.)?
At Tezzaron, we see two very distinict models. One for 25um pitch and higher and one for 10um pitch and lower. +25um is a chip to chip high density interconnect where as the -10um is a circuit level 3D realization.
Thanks for the details, Robert. One concern in all of this is terminology, so (just to be clear that we're using the same terms) does >25um pitch always mean "global" (between circuit blocks) interconnect and <10um always mean "local" (within a circuit block) for you?
We typically don't use those terms, but I think they are good. The 25um pitch I see as major function I/O, like memory to processor. The <10um is definately at a small functional block level, not gate to gate but ALU to register file type function.
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