Taller vs. Smaller Panel Report from the 2009 Lithography Workshop

By Karen Do On Jul. 09, 2009 Site: BrightSpots 3D IC Forum (Public) Type: Resource - Tags: 2D lithography | 3D IC integration | 3D lithography | ASML | BrightSpots | chip stacking | lithography | Lithography Workshop | Mentor Graphics | semiconductor | Semitool | Toshiba | VLSI Research - # of views: 4379

This is a summary from the Taller vs. Smaller panel discussion held July 1 at the 2009 Lithography Workshop on the interdependencies of 3D chip stacking and 2D lithographically-enabled feature shrinks, as reported by panel organizer Frank Schellenberg (Mentor Graphics).

Panelists Bill Arnold (ASML), Paul Franzon (NCSU), Iwao Higashikawa (Toshiba), and Erik Young (Semitool) were moderated at the live event by Dan Hutcheson (VLSI Research). The moderator for this online continuation of the discussion is Ed Korczynski (BetaSights).

Resource:

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