Lets start with the easiest. Speed. Scaling continues to make transistors faster, but wire, as we all know just gets slower. Physics just conspires against us here. The improvement in transistor performance is tiny compared to the slow down of the wire. To make wires faster, you need to make them shorter. 3D can do that far better than scaling and at a comparatively small cost.
With 3D you get power, density and cost also, but these require new approaches. Comingling of transistors and wire allows process separation leading to reduced costs. i.e. just build memory in the memory process, just build logic in a logic process. SOCs put a huge burden on processing. If you need flash, DRAM, and a processor on the same chip, you have a fab nightmare. The cost burden is huge. even thought neither the flash, nor DRAM, nor CPU cover the entire chip, the entire chip gets these processes applied to it. I like to say the foundry does offer a refund for under-utilized silicon area. With 3D, unecessary processing can be avoided, lowering cost and improving yield.
Density is a pretty obvious win. 4 layers of 45nm circuitry take about the same space as one 22nm device. By virtually any measure, development cost, fab facility cost, even piece part, 3D wins.
Power... The most straight forward is a simple look at where the power goes. If we assume high-k gates, and lower transistor leakage, most of the power is left in the charging and discharging of the wire. Make shorter wires...you get lower power. In our memories we make the wires half as long and we get a 40% reduction in per bit power.
I think in the end you need to look at what is the objective of scaling. Historically, it was performance, power, cost, and density. Performance was probably the driver for many years, at least for logic devices. For DRAM it most certainly was cost. Today, it is safe to say, we get no performance improvement from scaling. Power isn't improving. 3D can drive density faster than scaling. And the cost benefit from scaling is rapidly eroding. 22nm may be more costly than 45nm per transistor for sometime.
Don't get me wrong. I'm not predicting an end to scaling but I do see a major slow down. Fractional node advances are going to be the norm moving forward. The next decade or two will belong to 3D integration, just as the last has been the domain of CMOS. The exploitation of 3D has barely started. The opportunities go far beyond just connecting together the bond pads.
So if this is the case, why do companies continue to invest in scaling solutions or wirebond if the desired results can be achieved more efficiently with TSV?
Density and performance benefits are obvious , but I think heat dissipation is a major issue. Does anyone have any comments on methods of heat dissipation like thermal TSVs or use of high thermal conductivity substrates etc.
Because 3D requires new processes and new design paradigms to really reap the benefits, it scares people. The semiconductor industry is very conservative. There are huge investments at stake and this makes people risk adverse. Change = Risk, at least in peoples minds. The industry has 20+ years of shrinking CMOS success and every 2 years for the last 20, CMOS scaling was going to end...and it hasn't. Scaling isn't a cliff, it's just increasingly more difficult. Most people now see 3D as an option and the question is more of when is 3D going to be easier and or cheaper.
Heat is only as much of an issue in 3D as in 2D. The issue is getting the heat off of the die. A watt per sqmm of die surface seems to be a wall for conventional cooling. There have been at least a few efforts looking at thermal management in 3D with vias and smart layout. We haven't seen many actual devices that require this yet however. With the thin layers we use, there is little temperature difference from layer to layer. A typical application we see is adding a few watt memory to a 60-100 watt processor. The reduced I/O power (heat) exceeds the added heat load of the memory itself. That's not to say there is no issue stacking four 100W processors. I'm sure there is. But I don't think it is any more difficult than having a 400W 2d device.
Looking at this thermal issue another way, it is basically the same as scaling. If you scale from 45nm to 32nm and your die size is half, the thermal transfer to the heat sink must almost double per sqmm of die (as the power of our theorical device will remain almost unchanged by scaling). This is the same effect from cutting the original 45nm device in half and stacking the two layers.
Seeds for tools are planted, but there needs to be a driving reason for these to take off. In the near term, I don't see thermal a a show stopping issue for 3D
Sitaram Arkalgud addressed this during his presentation at last week's SEMATECH webcast. He pointed out that as a platform, 3D allows a whole other scheme of processes to be
considered that don’t enter the realm of possibilities when you’re
dealing with a 2D platform. Specifically, when it comes to thermal management, he said possible solutions involve using dummy TSVs as heat sinks; developing
design tools that dynamically detect where hotspots would be and
designing accordingly; or even incorporating channels for microfluidic
cooling. Sitaram - perhaps you could expand on this?
Additionally, i'm told that in general, thermal management isn't really an issue with memory applications, but is more of a concern with power devices and logic using 3D integration schemes.
Excellent points Bob. I see 3DIC as a potential means of making affordable "SOCs" thus enabling a whole new range of applications that are simply not economically viable today given the volumes required to justify a custom SOC design. I am also bullish on the potential of 3DIC for achieving ultra-low power electronics solutions, although serious design and architecture changes would be required to achieve this. This is the key challenge, getting folks to start thinking about the novel architectures that would be capable of exploiting 3DIC benefits. This will require CAD/EDA tools BEFORE killer apps are identified; quite an economic challenge.....
People will continue to invest in classical scaling "until the wheels fall off the bus" because this is percieved as a known risk path. Radically new architecture, circuit development or CAD tools are not required in this case. Of course, as problems continue to mount wrt classical scaling, more and more folks will be willing to consider 3DIC. At the moment the fraction of $'s being invested in 3DIC vs classical scaling is quite small. This will inevitably change.
In addition to thermally aware 3DIC design and thermal vias, I think that this technology opens up potential for novel inherently low power circuits and architectures as well as new parallelism opportunities. But this cannot be achieved by simply scaling today's standard digital cells.
I just came across an interesting read in the January 2009 issue of Chip Scale Review (pp. 24-27) that was written by Tom Adams about a research team at Georgia Tech that is working on a heat dissipation solution for 3D stack that combines electrical and fluidic TSVs in a stack.
I see 3D as a platform that can enable a whole new set of technologies. I agree with Bob and Mike on SoCs, since the industry has been struggling with cost vs complexity issues here for years. The most powerful argument in favor of 3D (assuming that the options are narrowed to a manageable few and the roadmaps and standards are in place) is that it permits the cost effective combination of dissimilar materials, technologies and signals. Replacing SoC with a 3D system in a stack is a low hanging fruit, but one could conceivably integrate optoelectronics and bio sensors with CMOS in a cost effective manner in the future.
As Bob said, heat dissipation will be as much an issue in 3D as it has been in 2D. However, Mike also brings up an important point, in that one of the benefits of 3D is a lower power consumption so less heat will be generated by the overall stack. However, the area available for disspation is now small compared to a 2D solution, so we will need to understand the issues (better modeling and simulation, especially of hot spots), control them (thermally aware layouts) and disspate the heat that does accumulate (die locations in the stack, heat sinks, thermal vias and cooling).
3D IC integration offers a myriad of
solutions to problems better than traditional scaling. According to Bob Patti, 3D IC with TSV interconnects offers increased speed and density for higher performance
at lower power and cost. He predicts that over the next decade or two 3D will
take the limelight from CMOS. "The exploitation of 3D has barely started," he
says. "The opportunities go far beyond just connecting together the bond pads."
However, because 3D requires new
processes and design paradigms, it scares people. The industry has 20+ years of
shrinking CMOS success, but it is becoming more difficult to achieve. Most
people now see 3D as an option and the question is more of when is 3D going to
be easier and or cheaper. The key challenge according to Michael Fritze of
DARPA is getting folks to start thinking about the novel architectures that
would be capable of exploiting 3DIC benefits.
Once processes have been narrowed to
a "manageable few", with roadmaps and standards in place, Sitaram Arkalgud says 3D IC integration permits the cost effective combination of
dissimilar materials, technologies and signals. He points out that when it comes to thermal
dissipation, lower power consumption of 3D stacks will result in less heat
generated, and additionally the 3D configurations lend themselves to new and
innovative methods of dissipating what heat exists.
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