3D InCites Technical Advisory Board

 

Deepak Sekar, Ph.D, Chief Scientist of Rambus Labs.

Deepak sekarDeepak Sekar is a Senior Principal Engineer at Rambus Labs, where he develops 3D non-volatile memory technologies. Until March 2012, he was the Chief Scientist of MonolithIC 3D Inc., a Silicon Valley startup selected as a Finalist of the Best of Semicon West 2011 for its innovative 3D technology. He managed MonolithIC 3D Inc.'s engineering and marketing teams and was an inventor or co-inventor of the company's 3D memory, logic and optoelectronic technologies. Sekar worked at SanDisk Corporation between 2006 and 2010, and developed rewritable memory devices, selector diodes and array architectures for 3D memories. His PhD research at the Georgia Institute of Technology involved doing some of the first experimental work on microchannel cooled 3D chips. He also developed a CAD tool called IntSim that simulates 2D and 3D chips. Sekar is the author of a book, an invited book chapter, 20 publications and 75 issued or pending patents. He has received numerous awards for his work,including two best paper awards and various Scholarships and Fellowships. He serves as a Program Committee Co-Chair at the International Interconnect Technology Conference and as a member of the Technical Advisory Board of 3D InCites, a web portal focused on 3D stacking. Sekar received a B. Tech from the Indian Institute of Technology (Madras) in 2003 and a PhD from the Georgia Institute of Technology in 2008.

Lee Smith, Chandler, AZ, Founder, Lee J. Smith Microelectronics

Former product marketing manager at Amkor Technologies Inc, Lee is a recognized industry expert in 3-D packaging, with 30 years of diverse technology and market development experience.  Over the past thirteen years he held 3-D packaging technology and business development responsibilities at Amkor, Texas Instruments, and Tessera with market emphasis in wireless handsets. Lee is recognized for leading the technology and infrastructure development of the widely adopted package-on-package (PoP) technology.  He successfully drove co-development of the supply chain to launch PoP into production, just fifteen months after defining the concept.  Lee has been instrumental in the infrastructure development for PoP including: JEDEC standards, SMT stacking, board level reliability and market adoption. He has authored or co-authored numerous patents, technical papers, and industry publications in advanced and 3-D packaging technologies as well as teaches 3-D packaging workshops at industry conferences. Lee is a member of IMAPS, SMTA and MEPTEC.

Sitaram R. Arkalgud, Ph.D., VP 3D technologies at Invensas Corp. 
 Sitaram Arkalgud is Vice President of 3D Technology at Invensas Corporation, a complete Interconnectology solutions provider for advanced mobile applications. Previously, Arkalgud started and led 3D IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for 3D interconnects. In addition, he has worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. Arkalgud holds a doctorate and master’s degree in materials engineering from Rensselaer Polytechnic Institute in Troy, NY, and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Suratkal, India. He is the author of several publications and holds 14 U.S. patents.

Nicolas Sillon, Ph.D. CEA-Leti Lab Manager for 3D Integration
Since 2004, Nicolas Sillon been in charge of the Packaging & Integration Technologies Laboratory at Leti, overseeing a staff of 50 people involved in developing wafer level technologies for MEMS packaging, CMOS Image Sensors & 3D integration.  He received a Ph.D.  from National Polytechnic Institute of Grenoble in 2001, developing a silicon micromachined mass spectrometer. He then joined CEA-Leti, working on MEMS manufacturing (RF MEMS, accelerometer) and MEMS packaging (thin film packaging and wafer level vacuum encapsulation) for 3 years. Since 2004, Sillon has authored or co-authored more than 50 papers in 3D integration & MEMS packaging area, including invited papers to major conferences like IEDM.

 

Erik Jan Marinissen, Principal Scientist at IMEC in Leuven, Belgium
Erik Jan Marinissen focuses his research in the domain of test and debug of integrated circuits. He is a co-author of more than 120 journal and conference papers and a co-inventor of eight granted US and EU patent families. Prior to IMEC, he was with NXP Semiconductors and Philips Research, both in Eindhoven, The Netherlands. He has received numerous awards for his work, including the Most Significant Paper Award at the IEEE International Test Conference in 2008. Marinissen served as an Editor-in-Chief of IEEE Std. 1500. He serves on numerous conference committees and editorial boards, and founded such workshops as 'Diagnostic Services in Network-on-Chips' (DSNOC) and '3D Integration'. He is a Senior Member of IEEE and a Golden Core Member of Computer Society. Marinissen holds a MSc degree in Computing Science a PDEng degree in Software Technology from Eindhoven University of Technology.

Yann Guillou, Business Development Manager, SEMI Europe Grenoble Office, France

Yann Guillou is Business Development Manager at SEMI Europe Grenoble Office. His main responsibilities encompass the development of SEMI activities in France & Southern Europe in Semiconductor, PV and Emerging markets and the coordination of SEMI standard activities in Europe. Previously, Yann worked on Advanced Packaging activities within the Back-End Sourcing and CTO & Strategic Planning office of ST-Ericsson. His main interest was 3D integration and TSV. He started his career at CEA-Leti before joining ST Microelectronics and successively worked at ST-NXP Wireless and ST Ericsson. Yann holds an MS in materials and nanotechnology from the National Institute of Applied Sciences and a master of management of technology and innovation from Grenoble Business School.